1. Technical Field
Various embodiments of the present disclosure relate generally to methods of evaluating exposure processes used in fabrication of semiconductor devices and, more particularly, to a method of controlling distortion of an exposure process.
2. Related Art
In the fabrication of semiconductor devices, a lithography process is typically performed for transferring images generated from patterns of a reticle onto a wafer. The lithography process may typically include coating a photoresist material on the wafer to form a photoresist layer, selectively exposing portions of the photoresist layer to a light passing through the reticle loaded into an exposure equipment, and developing the photoresist layer to selectively remove the exposed portions or the non-exposed portions of the photoresist layer. Circuit patterns of the semiconductor device may thus be realized on the wafer using the aforementioned exposure and development steps.
In the lithography process, an overlay margin between a first circuit pattern and a second circuit pattern aligned with the first circuit pattern has to be very accurately controlled to increase the fabrication yield of the semiconductor devices. The overlay margin refers to an alignment margin between two different layers which are stacked on the wafer. As semiconductor devices become more highly integrated, it has become increasingly more important to accurately and reliably control the overlay margin.